EDN

Streamlining the SoC Design Flow

In SoC design, a streamlined verification and analysis flow can contribute significantly to the success of a product. With manufacturing yield and time-to-market schedules crucial, it is important to ...
EDN

ESL-based flow eases complex SoC design

Deep-submicron technologies have clearly had a big impact on capacity and what can be designed on a single system-on-chip (SoC). With increased functionality, however, comes increased complexity for ...
Semiconductor Engineering

Crossing The Chasm: Uniting SoC And Package Verification

Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, ...
Nasdaq

Synopsys and Samsung Foundry Announce Reference Flow for Predictable Execution of ASIL D-Compliant SoC Design for Automotive Applications

Samsung Foundry and Synopsys' optimized flow achieves predictable execution of in-system test, implementation, verification, timing and physical signoff for ASIL D-compliant SoC design Includes ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of the industry’s first Verification IP (VIP) and System-Level VIP (System VIP) for the ...
Dataquest

Breker Verification Systems and Moores Lab AI partner to create first AI-driven SoC verification solution

Breker Verification Systems and Moores Lab AI formalized a partnership to create the first AI-driven SoC verification flow integrating Breker’s Trek Test Suite Synthesis with Moores Lab AI agentic AI ...
Embedded

Dealing with SoC hardware/software design complexity with scalable verification methods

The problem with today's existing methodologies is that verification issubservient to design. This principle requires a shift in paradigm,especially in designing complex electronic systems. Why?
Electronic Design

What’s the Deal with SoC Verification?

The title of this article may sound like the start of a Seinfeld joke from the 90s, but it’s actually a serious question. Many people do not appreciate what makes a system-on-chip (SoC) different from ...
Electronic Design

SystemC Advances Set the Stage For New SoC Design Flow Strategy

A new specification for Open Core Protocol (OCP) users will present a seamless flow for complex system-on-a-chip (SoC) designs. Publication of the spec comes via the OCP International Partnership (OCP ...