Huge transistor counts, rising on-chip clock rates, the relentlessly escalating levels of integration in systems-on-chip, and the new types of defects seen in deep-submicron and nanometer processes ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Anyone involved in IC product sign-off that includes a mixed signal design portion knows that developing robust tests for these intricate designs has historically been a significant bottleneck, no ...

Despite its standardization as IEEE 1149.1 in 1990 and wide use in the industry, many test engineers and developers still do not fully understand the benefits of boundary scan test. The misconceptions ...

At Alcatel-Lucent, we test chassis-level products that provide 42 board slots on a midplane, essentially a passive backplane that accepts boards on its front and rear sides. Thirty-four of those slots ...