Yahoo

Cadence Announces Tapeout of 14nm Test-Chip With ARM Processor and IBM FinFET Process Technology

SAN JOSE, CA--(Marketwire - Oct 30, 2012) - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today the tapeout of a 14-nanometer test-chip ...
Semiconductor Engineering

Low Power Trends Toward FinFET

Survey shows nearly a third of all designs are targeting the most advanced process nodes; 10nm tapeouts will happen right on the heels of 14/16nm. My previous blog, Power Reduction Techniques, covered ...
Design-Reuse

Synopsys and UMC Collaborate to Accelerate Development of UMC's 14-nm FinFET Process

HSINCHU, Taiwan and MOUNTAIN VIEW, Calif. -- June 26, 2013 -- Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic ...
Design-Reuse

ARM and TSMC Collaborate to Optimize Next-Generation 64-bit ARM Processors for FinFET Process Technology

Multi-year agreement drives alignment of next-generation processor, physical IP, and process technology for use in high-performance, energy-efficient mobile and enterprise markets Hsinchu, Taiwan and ...
EDN

All you need to know about GAA chip manufacturing process

The gate-all-around (GAA) semiconductor manufacturing process, also known as gate-all-around field-effect transistor (GAA-FET) technology, defies the performance limitations of FinFET by reducing the ...